The manufacture of Micro-Electro-Mechanical-Systems (MEMS), such as micro-gyroscopes, micro-accelerometers, resonant accelerometers, micro-mirrors, micro-motors, micro-actuators and other such micro-devices integrating at least one moving and/or particular component creates a very serious challenge for packaging for several reasons. The vast majority of MEMS-based devices require the encapsulation to be done before dicing, for protection against micro-contamination from particles and dicing slurry while being processed like a standard semiconductor chip, without the need for dedicated equipment or processes for dicing, mounting and molding procedures. Most MEMS-based resonant accelerometers, most MEMS-based RF switching devices and other such MEMS devices have Q-factors influenced by the operating pressure and then require a sealed package to ensure repeatable operating pressure. Changes in atmospheric conditions can also change the capacitance readout of micro-gyroscopes and micro-accelerometers without any rotation or acceleration. Increased relative humidity can increase the “stiction” and block the operation of moving mechanical parts.
A sealed package for encapsulating the moving and/or particular components in vacuum or in a controlled atmosphere in a sealed protection micro-cavity is thus necessary to ensure reliable operation. This micro-cavity is typically fabricated using microelectronic fabrication technologies so as to produce, on the wafer itself, a hermetic wafer-level package over each one of the various MEMS devices present on the wafer. Various approaches have been proposed to generate such a sealed wafer-level package, of which only a few allow a hermetic package. All references discussed below are incorporated herein by reference.
Wafer-level packaging of MEMS devices require the bonding of a so called “Lid wafer” to a so called “MEMS wafer” to form a sealed micro-cavity over each individual MEMS device of the “MEMS wafer”. Since the vacuum level or pre-set pressure in each micro-cavity must be maintained in the field for about 10 years, it is necessary to use sealing techniques and materials capable of preventing gas permeation from the external world to the interior of these micro-cavities. These requirements are similar to the ones required for sealing ultra-high vacuum systems.
FIG. 1 shows the permeability rates of classes of materials, going from the very poor materials (silicones and epoxies) to the ultra-high vacuum materials (metals). These generic curves show that glasses typically have about 1000 times the permeation rate of metals. This means that: the gaseous permeation through a 1 square meter of sheet metal of a given thickness is equivalent to the permeation rate of about 1 square millimeter of sheet glass of the same thickness. A given surface of sealing metal can be about 30 times thinner than the same surface of sealing glass and provide the same sealing performance against gaseous permeation (permeation is a diffusion mechanism following the square root function of the diffusion equation). A given thickness of sealing metal will provide 30 times longer life than the same thickness of sealing glass. For this reason, metal sealing techniques are generally preferred over glass sealing techniques.
The hermetic wafer-level packages should use the very low permeability characteristics of metal sealing materials for the wafer-level package to have a minimum gaseous permeation.
A first example of protective packaging is provided in FIG. 2 taken from the following cited Prior Art references: U.S. Pat. No. 5,323,051 titled ‘Semiconductor wafer level package’; U.S. Pat. No. 6,465,281 titled ‘Method of manufacturing a semiconductor wafer level package’; and Gary Li, Ampere A. Tseng, ‘Low stress packaging of a micromachined accelerometer’, IEEE Transactions on electronics packaging manufacturing, Vol. 24, No. 1, January 2001.
This wafer-level packaging technique involves the use of a frit glass, such as: EG9251 manufactured by Ferro Corporation; CF-8 manufactured by Nippon Electric Glass Co. Ltd; VIOX Glass No. 24925 manufactured by VIOX Corporation; and VIOX Glass No. 24927 manufactured by VIOX Corporation.
These flit glasses are typically deposited on the “Lid wafer” using a slurry comprising a mixture of organic binder, solvent, and a frit glass containing filler, deposited through a silk screen. Following printing and heating to a high enough temperature to volatilize the organic and organic materials of this slurry, the “Lid wafer” and the “MEMS wafer” are contacted and pressed together and exposed to high enough temperature (less than 550° C., preferably about 300° C.-475° C.) to exceed the softening point of the frit glass material and allow the thermo-compression bonding of the two wafers.
The two main challenges associated with this wafer-level packaging are, first, the induced mechanical stress in the MEMS devices of the “MEMS wafer” due to the mismatch of the thermal expansion coefficients of the materials of this wafer-level package which are exposed to the high temperatures used to reach the softening point of the frit glass and, second, the slow gas permeation and micro-porosity of the obtained frit material which result in a slow contamination of the sealed micro-cavity with hydrogen and water vapor. A wafer-level packaging process capable of producing a hermetic seal at temperatures lower than about 300° C. is preferred to minimize these induced mechanical stresses in the MEMS devices of the “MEMS wafer” and to ensure a stable gas composition in the sealed micro-cavity.
A second example of protective packaging is shown in FIG. 3 taken from the following cited Prior Art reference: U.S. Pat. No. 5,952,572 titled ‘Angular rate sensor and acceleration sensor’ (Matsushita Electric Industrial Co., Ltd.).
This technique requires the sodium atoms of a sodium-based silica glass (such as Coming Glass' Pyrex™ 7740) to be diffused at a temperature of about 300-450° C. and under a high electrical field created by a negative voltage of about 1000-2000V applied between the silicon substrate and the Pyrex™ substrate as to allow sodium displacement of the silicon atoms of the substrate and the anodic bonding of the Pyrex™ substrate to the silicon wafer. The anodic bonding temperature is not that lower than the one used for glass frit bonding and does not prevent the induced mechanical stresses in the MEMS devices of the “MEMS wafer”. Moreover, the sodium is an undesirable mobile ion inducing undesirable threshold voltage shifts of CMOS and high-voltage CMOS devices as well as dark-current issues in CCD devices.
The seed layer of“MEMS wafers” is typically the last electrically conductive layer deposited on the “MEMS wafer” and may either be a doped silicon layer or a metal layer.
The nickel under-layer structure of a wafer-level package can be made using electrolytic plating technologies to create the nickel under-layer structures of sealing rings on the “MEMS wafer” (around each individual die) and a symmetrical sealing rings on the “Lid wafer”. These two symmetrical nickel-based sealing rings allow the soldering of the “MEMS wafer” to the “Lid wafer” using a whisker-free solder (following proper alignment and physical contact of the symmetrical structures of the two wafers).
The main advantages of electrolytic plating of nickel under-layer structures are: accurate, low-cost, easy, and quick process; low-temperature process, compatible with the thermal budgets required to produce MEMS structures over CMOS and HV-CMOS devices; high aspect ratio under-layer structures when electroplated through very thick (10 μm to 1 mm) and narrow (one micron to a few microns) openings created using high-sensitivity photo-sensitive polymer exposed and developed with standard UV lithography and used as mold (a technique also called electro-forming).
The following Prior Art references describe an example of electrolytic plating of nickel structures used in MEMS applications: Hsin-chih Tim Yeh, “Fabrication and cooling test of high-aspect ratio electroplated micro-channels”, Master of Science in mechanical engineering, University of California Los Angeles, 1998; U.S. Pat. No. 6,411,754 titled ‘Micromechanical optical switch and method of manufacture’.
FIG. 4 is taken from U.S. Pat. No. 6,411,754 to Corning Incorporated and shows a MEMS-based photonics mirror obtained from electrolytic plating of nickel over a 0.5 μm thick evaporated copper seed layer and into a mold as to form an integral electrode structure. This 6 μm thick nickel layer is plated from a nickel sulfate solution at about 45° C.
In order to understand the limitations of nickel electrolytic plating for the formation of nickel under-structures, it is necessary to explain the basic principles of electrolytic plating. FIG. 5 is a sketch of a typical electrolytic plating set-up, called an electrolytic cell, where the MEMS wafer (or Lid wafer) is immersed in an electroplating solution to plate the electrolytic nickel under-structures. The anode provides the source of nickel and the chemical solution provides the cathode. The Ni2+ ions are neutralized by the electrons at the surface of the wafer.
This MEMS wafer (or Lid wafer) is connected to a negative potential relative to a positive electrode typically consisted of the electroplating nickel metal anode that is also immersed in the plating solution. If sufficient bias is imposed between the two electrodes, electrons will flow through the power supply from the anode (the nickel electrode) to the cathode (the surface of exposed conductor of the wafer in contact with the plating solution). Near the cathode, a reduction reaction (gain of electron) occurs, resulting in the plating of a nickel under-structure onto the exposed surface:Ni2+→2e−+Ni
This reduction mechanism requires an electrical current to be continuously supplied to the growing nickel under-structure so as to neutralize, at the surface, the incoming Ni2+ ions supplied by the plating solution.
On the other hand, inside the electroplating solution, the current is conducted by the flow of positive ions and an oxidation reaction (loss of electrons) occurs near the nickel anode:Ni→2e−+Ni2+where the nickel atoms of the anode are dissolved into the plating solution. This reaction supplied the two electrons flowing into the power supply and the nickel ion migrating into the solution toward the wafer cathode. The supplied current controls the neutralization rate and then the flow of migrating nickel ions, i.e. the electrolytic plating rate.
Some hydrogen reduction also occurS near the wafer (cathode) surface:2H++2e−→H2
This hydrogen reduction reaction competes with the nickel deposition and should be avoided. An excess amount of hydrogen also deteriorates the quality of plated nickel.
Since the electrolytic plating of nickel under-structures requires the neutralization surfaces to be electrically connected to the power supply, an electrically isolated surface will not be plated. This simple mechanism allows the selective electrolytic plating of nickel under-structures over electrically conductive surfaces exposed through openings in dielectrics, such as photoresists.
FIG. 6 shows an example of electroplating process resulting in the selective formation of nickel under-structures through a polymer pattern on a flat surface wafer. The process consists of the following steps:    1: Provision of a MEMS device    2: Sacrificial layer deposition    3: Structural layer deposition    4: Continuous unbroken seed layer deposition    5: Polymer deposition, exposure, development    6: Selective nickel electrolytic plating over the continuous and unbroken seed layer in exposed regions of the polymer pattern,    7: Removal of patterned polymer in an oxygen-containing ambient (resulting in undesirable nickel oxidation)    8: Removal of the continuous and unbroken seed layer in the regions previously coated by the polymer (resulting in undesirable undercut due to the need to ensure complete elimination of the electrically conductive seed layer between the nickel patterns)
In order to selectively plate the nickel under-structures in all exposed openings of the polymer, it is necessary to electrically shunt these exposed surfaces using a “continuous and unbroken seed layer” which allows the continuous neutralization of the impinging Ni2+ ions on these exposed surfaces. Following electrolytic plating and polymer removal in an oxygen-containing ambient (resulting in undesirable surface oxidation of the nickel under-structures and uncontrolled soldering, a situation to be addressed later in the disclosure of this invention) this electrical shunt “continuous and unbroken seed layer” has to be removed; otherwise it would result in electrically shorted nickel under-structures. This removal is relatively simple if a selective etch can remove this “continuous and unbroken seed layer” from the areas previously coated with the polymer without attacking the plated nickel under-structures. The complete removal of this “unbroken and continuous seed layer” from the areas previously coated with the polymer is not obvious on the non-flat surface of an advanced MEMS wafer already presenting high aspect ratio structures and topography.
FIG. 7 shows an example of an electroplating process over the non-flat surface of an advanced MEMS wafer presenting high aspect-ratio structures and topography. This process consists of the following steps:    1: Provision of MEMS substrate    2: Sacrificial layer deposition and patterning to open structural layer anchors to substrate    3: Structural layer deposition and patterning    4: Continuous and unbroken seed layer deposition (difficult seed layer coverage on the sidewalls of topography: More topography means worse coverage and poorer local electrical conductivity)    5: Polymer deposition, exposure, develop (difficult to fill high aspect ratio regions with polymer where a minimum gap is present between two adjacent surfaces of the continuous and unbroken seed layer, thus resulting in potential undesirable loss of adhesion of polymer and undesirable plating)    6: Selective nickel electrolytic plating over the continuous and unbroken seed layer in exposed regions of the polymer pattern    7: Removal of patterned polymer in an oxygen-containing ambient (thus resulting in undesirable nickel oxidation)    8: Removal of exposed continuous and unbroken seed layer in the region previously coated by the polymer (thus resulting in undesirable undercut due to the need to ensure complete elimination of this electrically conductive seed layer between the nickel patterns)    9: Mechanical release of the suspended structures by removal of the sacrificial layer (Very little remaining seed layer in the anchors region combined with the need to have this remaining seed layer resisting the chemicals used for this mechanical release)
In this case, the sacrificial layer is patterned such as to create openings or anchors of the nickel under-structures to the substrate (or to any other non-sacrificial layer) and as to later allow the mechanical release of non-anchored structures. Advanced MEMS use thicker and narrower suspended structures and multi-level structures with smaller spacings as to enhance electrostatic sensing and actuation. This means that the “continuous and unbroken seed layer” is to be deposited as thin as possible (as to minimize the undercut resulting from its local removal later in the process) on increasingly complex high aspect ratio structures. The need to maintain good coverage of the “continuous and unbroken seed layer” on the sidewall of these increasing aspect ratio structures (as to provide the electrical conductivity needed to sustain the electrolytic plating of the nickel under-structures) while minimizing the thickness of the “continuous and unbroken seed layer” under the anchored structures (as to prevent excessive undercut) and while ensuring an absolute elimination of the “continuous and unbroken seed layer” in the deeper-and-narrower trenches located between electrically isolated nickel under-structures following polymer removal, dictates that the electrolytic nickel plating technique using a seed layer has limited applications in the manufacturing of advanced MEMS devices.
It is clear that the electrolytic plating of nickel under-structures is undesirable for advanced MEMS devices and for their wafer-level packages because the use of a seed layer is undesirable for these advances MEMS devices.